1. Field of the Invention
The present invention relates to a semiconductor memory device and a computer, and in particular to a semiconductor memory device which produces a signal indicative of the fact that output is fixed in the operation of outputting stored data as well as a computer provided with this semiconductor memory device.
The semiconductor memory device according to the invention is applicable to any kinds of computer such as a super computer, a large scale computer, a work station and a personal computer.
2. Description of the Related Art
FIG. 1 shows a conventional semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In FIG. 1, an RAM (Random Access Memory) 1 receives address signals A.sub.0, A.sub.1, . . . as well as a control signal CTR which includes a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE, if it is a DRAM, or control signal CTR includes a chip select signal CS and a write enable signal WE, if it is an SRAM. In accordance with a state of control signal CTR, RAM 1 writes externally applied input data D.sub.in, into memory cells selected by address signals A.sub.0, A.sub.1, . . . , or reads potentials corresponding data stored in memory cells selected by address signals A.sub.0, A.sub.1, . . . for externally applying the same as output data D.sub.out.
A read operation of the conventional semiconductor memory device thus constructed will be described below with reference to timing charts of FIGS. 2 and 3. FIG. 2 is the timing chart showing the read operation in the case where RAM 1 is the SRAM. In the read operation, chip select signal CS is set to the L-level as shown at (a) in FIG. 2 to activate the SRAM, and write enable signal WE is set to the H-level as shown at (b) in FIG. 2. Externally applied address signals A.sub.0, A.sub.1, . . . change at time t.sub.0 as shown at (c) in FIG. 2.
In accordance with data stored in the memory cells selected by address signals A.sub.0, A.sub.1, . . . , output data D.sub.out changes its state, as shown at (d) in FIG. 2, from a high impedance (Hi-Z) state to the H-level or L-level at time t.sub.1 when an address access time t.sub.AAC (e.g., 10 ns) elapses from the time to of change of address signals A.sub.0, A.sub.1, . . . When chip select signal CS is set to the H-level at time t.sub.2 as shown at (a) in FIG. 2, the SRAM is deactivated, and output data D.sub.out attains the high impedance (Hi-Z) state again as shown at (d) in FIG. 2.
FIG. 3 is the timing chart showing the read operation in the case where RAM 1 is the DRAM. Before time t.sub.0 at which row address strobe signal RAS falls to the L-level as shown at (a) in FIG. 3, address signals A.sub.0, A.sub.1, . . . are set to the X-address of the memory cell to be selected as shown at (d) in FIG. 3. When row address strobe signal RAS falls to the L-level at time to as shown at (a) in FIG. 3, the DRAM responding it takes in and latches the same using address signals A.sub.0, A.sub.1, . . . as the X-address. Then, write enable signal WE is set to the H-level at time t.sub.1 as shown at (c) in FIG. 3, and the DRAM responds to the same and is controlled to perform the reading.
Column address strobe signal CAS is raised to the L-level at time t.sub.3 as shown at (b) in FIG. 3. At time t.sub.2 preceding time t.sub.2, address signals A.sub.0, A.sub.1, . . . are set to the Y-address of the memory cell to be selected as shown at (d) in FIG. 3. Column address strobe signal CAS falls to the L-level at time t.sub.3 as shown at (b) in FIG. 3. In accordance with data stored in the memory cell selected by the X-address and Y-address, output data D.sub.out changes its state from the high impedance (Hi-Z) state to the H-level or L-level at time t.sub.4 after elapsing of an RAS access time t.sub.RAS (e.g., 50 ns) from time t.sub.0 and hence after elapsing of a CAS access time t.sub.CAS from time t.sub.3. When column address strobe signal CAS is raised to the H-level at time t.sub.5 as shown at (b) in FIG. 3, output data D.sub.out attains the high impedance (Hi-Z) state again as shown at (e) in FIG. 3.
In the conventional semiconductor memory device thus constructed, the specification of RAM prescribes the maximum access times (t.sub.AAC (max), t.sub.RAS (max), t.sub.CAS (max) and others) in connection with the access time. The specification also prescribes the operation conditions of RAM. For example, a prescribed power supply potential is 5V.+-.10% (4.5 V-5.5 V), and a prescribed operation temperature is from 0.degree. C. to 70.degree. C.
The access time of RAM mainly depends on the performance of transistors forming the RAM. In general, a current drive capability of the MOS transistor decreases as the power supply potential decreases, and also decreases as the operation temperature decreases. The operation speed decreases as the current drive capability decreases. The maximum access time is equal to the access time required under the worst environmental conditions of RAM, i.e., at a low power supply potential in a high temperature.
When designing the timing of a system using a conventional RAM, the designed access time must be equal to the maximum access time in view of a margin for allowing use or operation under the worst conditions of a low power supply potential and a high temperature, even if the system will not be used under the worst conditions in practice. Therefore, in spite of the fact that the actual access time can be shorter than the maximum access time unless it is used under the worst conditions, the speed of the system is unduly low due to the timing margin determined in view of the use under the worst conditions.
In a system operating in synchronization with a clock of a fixed frequency, it is necessary to design the system to operate with a low frequency allowing correct operation of the RAM under the worst conditions of the system. In practice, the system may not be used under the worst conditions. Even in such a case that the system can be operated at a higher speed because, e.g., the RAM can be accessed at a higher speed, the system must actually operate at the low speed as if it were operating under the worst conditions due to the fact that the clock frequency is fixed, so that the system speed is unduly reduced.